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mcm69r737a ? mcm69r819a 1 motorola fast sram advance information 4m late write lvttl the mcm69r737a/819a is a 4 megabit synchronous late write fast static ram designed to provide high performance in secondary cache and atm switch, telecom, and other high speed memory applications. the mcm69r819a organized as 256k words by 18 bits, and the mcm69r737a organized as 128k words by 36 bits wide are fabricated in motorola's high performance silicon gate bicmos technology. the differential ck clock inputs control the timing of read/write operations of the ram. at the rising edge of the ck clock all addresses, write enables, and synchronous selects are registered. an internal buffer and special logic enable the memory to accept write data on the rising edge of the ck clock a cycle after address and control signals. read data is driven on the rising edge of the ck clock also. the ram uses lvttl 3.3 v inputs and outputs. the synchronous write and byte enables allow writing to individual bytes or the entire word. ? byte write control ? single 3.3 v + 10%, 5% operation ? lvttl 3.3 v i/o (v ddq ) ? register to register synchronous operation ? asynchronous output enable ? boundary scan (jtag) ieee 1149.1 compatible ? differential clock inputs ? optional x 18 or x 36 organization ? mcm69r737a/819a5 = 5 ns mcm69r737a/819a6 = 6 ns mcm69r737a/819a7 = 7 ns mcm69r737a/819a8 = 8 ns ? sleep mode operation (zz pin) ? 119 bump, 50 mil (1.27 mm) pitch, 14 mm x 22 mm plastic ball grid array (pbga) package this document contains information on a new product. specifications and information herein are subject to change without notice. order this document by mcm69r737a/d semiconductor technical data mcm69r737a mcm69r819a zp package pbga case 99901 rev 1 8/13/97 ? motorola, inc. 1997
mcm69r737a ? mcm69r819a 2 motorola fast sram address registers sa ck sw sbx control logic data in register memory array g sw registers data out register dq ss ss registers functional block diagram pin assignments mcm69r737a 6 5 4 3 2 17 b c v ss g a d e f h j v ss v ss sbb v ss sa v ss v ss v ss sa sa sa sa sa sa sa sa nc sa sa nc nc nc dqb sa sa nc zz sw dqa dqa v ddq v ddq dqb v ddq dqb dqb dqa dqa v dd v dd tdo sa tdi tms nc tck dqd dqd v ss sa ck v ss dqa dqa sa v ss dqd dqd v ddq dqd v ss nc dqa dqa sba sbd dqd dqd dqd dqd v ss ck v ss dqc dqa v dd nc v dd nc v dd v ddq dqc v ss nc dqb dqb dqb nc sbc dqc dqc v ddq dqc v ss g dqb ss v ss dqc dqc dqc v ss nc dqb v dd nc nc nc sa nc nc k l m n p r t u v ddq v ddq nc v ddq v ddq nc 6 5 4 3 2 17 b c v ss g a d e f h j v ss v ss v ss v ss sa v ss v ss v ss sa sa sa sa sa sa sa sa sa sa sa sa nc nc nc sa sa nc zz sw nc nc v ddq v ddq nc v ddq dqa dqa dqa dqa v dd v dd tdo nc tdi tms nc tck nc dqb v ss sa ck v ss nc dqa sa v ss nc dqb v ddq dqb v ss nc nc dqa sba v ss nc dqb nc dqb v ss ck v ss dqb nc v dd nc v dd nc v dd v ddq nc v ss nc dqa dqa nc nc sbb dqb nc v ddq nc v ss g nc ss v ss dqb nc dqb nc v ss nc dqa v dd nc nc nc sa nc nc k l m n p r t u v ddq v ddq nc v ddq v ddq nc mcm69r819a dqc top view
mcm69r737a ? mcm69r819a 3 motorola fast sram mcm69r737a pin descriptions pbga pin locations symbol type description 4k ck input address, data in and control input register clock. active high. 4l ck input address, data in and control input register clock. active low. (a) 6k, 7k, 6l, 7l, 6m, 6n, 7n, 6p, 7p (b) 6d, 7d, 6e, 7e, 6f, 6g, 7g, 6h, 7h (c) 1d, 2d, 1e, 2e, 2f, 1g, 2g, 1h, 2h (d) 1k, 2k, 1l, 2l, 2m, 1n, 2n, 1p, 2p dqx i/o synchronous data i/o. 4f g input output enable: asynchronous pin, active low. 2a, 3a, 5a, 6a, 3b, 5b, 2c, 3c, 5c, 6c, 4n, 4p, 2r, 6r, 3t, 4t, 5t sa input synchronous address inputs: registered on the rising clock edge. 5l, 5g, 3g, 3l (a), (b), (c), (d) sbx input synchronous byte write enable: enables writes to byte x in conjunction with the sw input. has no effect on read cycles, active low. 4e ss input synchronous chip enable: registered on the rising clock edge, active low. 4m sw input synchronous write: registered on the rising clock edge, active low. writes all enabled bytes. 4u tck input test clock (jtag). 3u tdi input test data in (jtag). 5u tdo output test data out (jtag). 2u tms input test mode select (jtag). 7t zz input enables sleep mode, active high. 4c, 2j, 4j, 6j, 4r, 5r v dd supply core power supply. 1a, 7a, 1f, 7f, 1j, 7j, 1m, 7m, 1u, 7u v ddq supply output power supply: provides operating power for output buffers. 3d, 5d, 3e, 5e, 3f, 5f, 3h, 5h, 3k, 5k, 3m, 5m, 3n, 5n, 3p, 5p, 3r v ss supply ground. 4a, 1b, 2b, 4b, 6b, 7b, 1c, 7c, 4d, 4g, 4h, 3j, 5j, 1r, 7r, 1t, 2t, 6t, 6u nc e no connection: there is no connection to the chip. note: 3j and 5j are tied common.
mcm69r737a ? mcm69r819a 4 motorola fast sram mcm69r819a pin descriptions pbga pin locations symbol type description 4k ck input address, data in and control input register clock. active high. 4l ck input address, data in and control input register clock. active low. (a) 6d, 7e, 6f, 7g, 6h, 7k, 6l, 6n, 7p (b) 1d, 2e, 2g, 1h, 2k, 1l, 2m, 1n, 2p dqx i/o synchronous data i/o. 4f g input output enable: asynchronous pin, active low. 2a, 3a, 5a, 6a, 3b, 5b, 2c, 3c, 5c, 6c, 4n, 4p, 2r, 6r, 2t, 3t, 5t, 6t sa input synchronous address inputs: registered on the rising clock edge. 5l, 3g (a), (b) sbx input synchronous byte write enable: enables writes to byte x in conjunction with the sw input. has no effect on read cycles, active low. 4e ss input synchronous chip enable: registered on the rising clock edge, active low. 4m sw input synchronous write: registered on the rising clock edge, active low. writes all enabled bytes. 4u tck input test clock (jtag). 3u tdi input test data in (jtag). 5u tdo output test data out (jtag). 2u tms input test mode select (jtag). 7t zz input enables sleep mode, active high. 4c, 2j, 4j, 6j, 4r, 5r v dd supply core power supply. 1a, 7a, 1f, 7f, 1j, 7j, 1m, 7m, 1u, 7u v ddq supply output power supply: provides operating power for output buffers. 3d, 5d, 3e, 5e, 3f, 5f, 5g, 3h, 5h, 3k, 5k, 3l, 3m, 5m, 3n, 5n, 3p, 5p, 3r v ss supply ground. 4a, 1b, 2b, 4b, 6b, 7b, 1c, 7c, 2d, 4d, 7d, 1e, 6e, 2f, 1g, 4g, 6g, 2h, 4h, 7h, 3j, 5j, 1k, 6k, 2l, 7l, 6m, 2n, 7n, 1p, 6p, 1r, 7r, 1t, 4t, 6u nc e no connection: there is no connection to the chip. note: 3j and 5j are tied common.
mcm69r737a ? mcm69r819a 5 motorola fast sram absolute maximum ratings (voltages referenced to v ss , see note 1) rating symbol value unit core supply voltage v dd 0.5 to + 4.6 v output supply voltage v ddq 0.5 to v dd + 0.5 v voltage on any pin v in 0.5 to v dd + 0.5 v input current (per i/o) i in 50 ma output current (per i/o) i out 70 ma power dissipation (see note 2) p d e w operating temperature t a 0 to + 70 c temperature under bias t bias 10 to + 85 c storage temperature t stg 55 to + 125 c notes: 1. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended oper- ating conditions. exposure to higher than recommended voltages for extended periods of time could affect device reliability. 2. power dissipation capability will be dependent upon package characteristics and use environment. see enclosed thermal impedance data. pbga package thermal characteristics rating symbol max unit notes junction to ambient (still air) r q ja 53 c/w 1, 2 junction to ambient (@200 ft/min) single layer board r q ja 38 c/w 1, 2 junction to ambient (@200 ft/min) four layer board r q ja 22 c/w junction to board (bottom) r q jb 14 c/w 3 junction to case (top) r q jc 5 c/w 4 notes: 1. junction temperature is a function of onchip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. per semi g3887. 3. indicates the average thermal resistance between the die and the printed circuit board. 4. indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec883 method 1012.1). clock truth table k zz ss sw sba sbb sbc sbd dq (n) dq (n+1) mode l h l l h x x x x x d out 035 read cycle all bytes l h l l l l h h h highz d in 08 write cycle 1st byte l h l l l h l h h highz d in 917 write cycle 2nd byte l h l l l h h l h highz d in 1826 write cycle 3rd byte l h l l l h h h l highz d in 2735 write cycle 4th byte l h l l l l l l l highz d in 035 write cycle all bytes l h l l l h h h h highz highz abort write cycle l h l h h x x x x x highz deselect cycle l h l h l x x x x highz highz deselect cycle x h x x x x x x highz highz sleep mode this device contains circuitry to protect the inputs against damage due to high static volt- ages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maxi- mum rated voltages to this highimpedance circuit. this bicmos memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. this device contains circuitry that will ensure the output devices are in highz at power up.
mcm69r737a ? mcm69r819a 6 motorola fast sram dc operating conditions and characteristics (0 c t a 70 c, unless otherwise noted) recommended operating conditions (see notes 1 through 4) parameter symbol min typical 5 typical 6 typical 7 typical 8 max unit notes core power supply voltage v dd 3.15 e e e e 3.6 v output driver supply voltage v ddq 3.15 e e e e 3.6 v active power supply current (x18) (x36) i dd1 e e 380 450 360 420 330 390 320 370 480 550 ma 5 quiescent active power supply current i dd2 e e 180 180 180 180 250 ma 6, 10 active standby power supply current) i sb1 e e 170 170 170 170 250 ma 7 quiescent standby power supply current i sb2 e e 150 150 150 150 230 ma 8, 10 sleep mode power supply current i sb3 e 30 30 30 30 50 ma 9, 10 notes: 1. all data sheet parameters specified to full range of v dd unless otherwise noted. all voltages are referenced to voltage applied to v ss bumps. 2. supply voltage applied to v dd connections. 3. supply voltage applied to v ddq connections. 4. all power supply currents measured with outputs open or deselected. 5. v dd = v dd (max), t khkh = t khkh (min), ss registered active, 50% read cycles. 6. v dd = v dd (max), t khkh = dc, ss registered active. 7. v dd = v dd (max), t khkh = t khkh (min), ss registered inactive. 8. v dd = v dd (max), t khkh = dc, ss registered inactive. zz low. 9. v dd = v dd (max), t khkh = dc, ss registered inactive, zz high. 10. 200 mv v in v ddq 200 mv. dc input characteristics parameter symbol min max unit notes dc input logic high v ih (dc) 2.0 v dd + 0.3 v dc input logic low v il (dc) 0.3 0.8 v 1 input leakage current i lkg(1) e 5 m a 2 clock input leakage current i clkg(1) e 8 m a 2 clock input signal voltage v in 0.3 v dd + 0.3 v clock input differential voltage v dif (dc) 0.2 v dd + 0.6 v 3 clock input common mode voltage range (see figure 3) v cm (dc) 1 2.1 v 4 notes: 1. inputs may undershoot to 0.5 v (peak) for up to 20% t khkh (e.g., 2 ns at a clock cycle time of 10 ns). 2. 0 v v in v ddq for all pins. 3. minimum instantaneous differential input voltage required for differential input clock operation. 4. maximum rejectable common mode input voltage variation. dc output characteristics parameter symbol min max unit notes output leakage current i lkg(0) 1.0 1.0 m a output low voltage v ol e 0.4 v 1 output high voltage v oh 2.4 e v 2 notes: 1. i ol = 8.0 ma. 2. i oh = 8.0 ma.
mcm69r737a ? mcm69r819a 7 motorola fast sram capacitance (f = 1.0 mhz, dv = 3.0 v, 0 c t a 70 c, periodically sampled rather than 100% tested) characteristic symbol typ max unit input capacitance c in 4 5 pf input/output capacitance c i/o 7 8 pf ck, ck capacitance c ck 4 5 pf ac operating conditions and characteristics (0 c t a 70 c, unless otherwise noted) input pulse levels 0 to 3.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input rise/fall time 1 v/ns (20% to 80%) . . . . . . . . . . . . . . . . . . . . . . input timing measurement reference level 1.5 v . . . . . . . . . . . . . . . output timing reference level 1.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . clock input timing reference level differential crosspoint . . . . . . clock input pulse level 1.8 v to 2.1 v . . . . . . . . . . . . . . . . . . . . . . . . . r q ja tbd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . read/write cycle timing (see note 1) mcm69r737a5 mcm69r819a5 mcm69r737a6 mcm69r819a6 mcm69r737a7 mcm69r819a7 mcm69r737a8 mcm69r819a8 parameter symbol min max min max min max min max unit notes cycle time t khkh 5 e 6 e 7 e 8 e ns clock high pulse width t khkl 2 e 2.4 e 2.8 e 3.2 e ns clock low pulse width t klkh 2 e 2.4 e 2.8 e 3.2 e ns clock high to output lowz t khqx1 1 e 1 e 1 e 1 e ns 2,3 clock high to output valid t khqv e 2.5 e 3 e 3.5 e 3.5 ns clock high to output hold t khqx 0.5 e 0.5 e 0.5 e 0.5 e ns clock high to output highz t khqz e 2.5 e 3 e 3.5 e 3.5 ns 2, 3 output enable low to output lowz t glqx 0.5 e 0.5 e 0.5 e 0.5 e ns output enable low to output valid t glqv e 2.5 e 3 e 3.5 e 3.5 ns output enable to output hold t ghqx 0.5 e 0.5 e 0.5 e 0.5 e ns output enable high to output highz t ghqz e 2.5 e e 3.5 e 3.5 ns 2, 3 setup times: address data in chip select write enable t avkh t dvkh t svkh t wvkh 0.5 e 0.5 e 0.5 e 0.5 e ns hold times: address data in chip select write enable t khax t khdx t khsx t khwx 1 e 1 e 1 e 1 e ns notes: 1. in no case may control input signals (e.g., ss ) be operated with pulse widths less than the minimum clock input pulse width specifications (e.g., t khkl ) or at frequencies that exceed the applied k clock frequency. 2. this parameter is sampled and not 100% tested. 3. measured at 200 mv from steady state.
mcm69r737a ? mcm69r819a 8 motorola fast sram the table of timing values shows either a minimum or a maximum limit for each param- eter. input requirements are specified from the external system point of view. thus, ad- dress setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). on the other hand, responses from the memory are specified from the device point of view. thus, the access time is shown as a maximum since the device never pro- vides data later than that time. timing limits device under test 50 w 50 w v ddq /2 figure 1. ac test load v oh v ss 50% 100% 20% t khkh figure 2. undershoot voltage crossing point v ddq v ss v tr v dif v cp v cm * figure 3. differential inputs/common mode input voltage *v cm , the common mode input voltage, equals v tr ((v tr v cp )/2).
mcm69r737a ? mcm69r819a 9 motorola fast sram t khkl t khkh dqx ck q1 sa a0 a1 register/register readwriteread cycles t klkh q0 q1 t khqv d2 q3 t khqz a2 a3 a4 t khqx1 t khdx t dvkh t wvkh t khwx t svkh t khsx t avkh t khax v il ss sw sbx g t khqx
mcm69r737a ? mcm69r819a 10 motorola fast sram t khkl t khkh dqx ck q1 sa a0 a1 t klkh q0 q1 d2 q3 t ghqz a2 a3 a4 t glqx t avkh t khax v il t ghqx t glqv register/register readwriteread (g controlled) ss sw sbx g
mcm69r737a ? mcm69r819a 11 motorola fast sram functional operation read and write operations all control signals except g are registered on the rising edge of the ck clock. these signals must meet the setup and hold times shown in the ac characteristics table. on the rising edge of the following clock, read data is clocked into the output register and available at the outputs at t khqv . dur- ing this same cycle a new read address can be applied to the address pins. a deselect cycle (dead cycle) must occur prior to a write cycle. read cycles may follow write cycles immediately. g , ss , and sw control output drive. chip deselect via a high on ss at the rising edge of the ck clock has its effect on the output drivers after the next rising edge of the ck clock. sw low deselects the output drivers immediately (on the same cycle). output selecting via a low on ss and high on sw at a rising ck clock has its effect on the output drivers after the next rising edge of the ck clock. output drive is also controlled directly by output enable, g . g is an asynchronous input. no clock edges are required to enable/disable the out- put using g . output data will be valid the latter of t glqv and t khqv . out- puts will begin driving at t khqx1 . outputs will hold previous data until t khqx or t ghqx . write and byte write functions note that in the following discussion the term abyteo refers to nine bits of the ram i/o bus. in all cases, the timing pa- rameters described for synchronous write input (sw ) apply to each of the byte write enable inputs (sba , sbb , etc.). byte write enable inputs have no effect on read cycles. this allows the system designer not interested in performing byte writes to connect the byte enable inputs to active low (v ss ). reads of all bytes proceed normally and write cycles, activated via a low on sw , and the rising edge of the ck clock, write the entire ram i/o width. this way the designer is spared having to drive multiple write input buffer loads. byte writes are performed using the byte write enable in- puts in conjunction with the synchronous write input (sw ). it is important to note that writing any one byte will inhibit a read of all bytes at the current address. the ram cannot simulta- neously read one byte and write another at the same ad- dress. a write cycle initiated with none of the byte write enable inputs active is neither a read or a write. no write will occur, but the outputs will be deselected as in a normal write cycle. late write the write address is sampled on the first rising edge of clock and write data is sampled on the following rising edge. the late write feature is implemented with single stage write buffering. write buffering is transparent to the user. a comparator monitors the address bus and, when necessary, routes buffer contents to the outputs to assure coherent op- eration. this occurs in all cases whether there is a byte write or a full word is written. power up and initialization the following supply voltage application sequence is rec- ommended: v ss , v dd , then v ddq . please note, per the ab- solute maximum ratings table, v ddq is not to exceed v dd + 0.5 v, whatever the instantaneous value of v dd . once sup- plies have reached specification levels, a minimum dwell of 1.0 ms with c/k clock inputs cycling is required before begin- ning normal operations. at power up the output impedance will be set at approximately 50 w as stated above.
mcm69r737a ? mcm69r819a 12 motorola fast sram serial boundary scan test access port operation overview the serial boundary scan test access port (tap) on this ram is designed to operate in a manner consistent with ieee standard 1149.11990 (commonly referred to as jtag), but does not implement all of the functions required for 1149.1 compliance. certain functions have been modified or eliminated because their implementation places extra de- lays in the rams critical speed path. nevertheless, the ram supports the standard tap controller architecture. (the tap controller is the state machine that controls the taps opera- tion) and can be expected to function in a manner that does not conflict with the operation of devices with standard 1149.1 compliant taps. the tap operates using convention- al jedec standard 81b low voltage (3.3 v) ttl / cmos logic level signaling. disabling the test access port it is possible to use this device without utilizing the tap. to disable the tap controller without interfering with normal op- eration of the device, tck must be tied to v ss to preclude mid level inputs. tdi and tms are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. but they may also be tied to v dd through a 1 k resistor. tdo should be left uncon- nected. tap dc operating characteristics (0 c t a 70 c, unless otherwise noted) parameter symbol min max unit note logic input logic high v ih 1 2.0 v dd + 0.3 v logic input logic low v il 1 0.3 0.8 v logic input leakage current i lkg e 5 m a 1 cmos output logic low v ol 1 e 0.2 v 2 cmos output logic high v oh 1 v dd 0.2 e v 3 ttl output logic low v ol 2 e 0.4 v 4 ttl output logic high v oh 2 2.4 e v 5 notes: 1. 0 v v in v ddq for all logic input pins. 2. i ol 1 100 m a @ v ol = 0.2 v. sampled, not 100% tested. 3. |i oh 1| 100 m a @ v ddq 0.2 v. sampled, not 100% tested. 4. i ol 2 8 ma @ v ol = 0.4 v. 5. |i oh 2| 8 ma @ v oh = 2.4 v.
mcm69r737a ? mcm69r819a 13 motorola fast sram tap ac operating conditions and characteristics (0 c t a 70 c, unless otherwise noted) input pulse levels 0 to 3.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input rise/fall time 1 v/ns (20% to 80%) . . . . . . . . . . . . . . . . . . . . . . input timing measurement reference level 1.5 v . . . . . . . . . . . . . . . output timing reference level 1.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . output test load 50 w parallel terminated tline with 20 pf . . . . . . receiver input capacitance test load termination supply voltage (v t ) 1.5 v . . . . . . . . . . . . . . . tap controller timing parameter symbol min max unit notes cycle time t thth 100 e ns clock high time t thtl 40 e ns clock low time t tlth 40 e ns tms setup t mvth 10 e ns tms hold t thmx 10 e ns tdi valid to tck high t dvth 10 e ns tck high to tdi don't care t thdx 10 e ns capture setup t cs 10 e ns 1 capture hold t ch 10 e ns 1 tck low to tdo unknown t tlqx 0 e ns tck low to tdo valid t tlov e 20 ns notes: 1. t cs + t ch defines the minimum pause in ram i/o pad transitions to assure accurate pad data capture. ac test load device under test 50 w 50 w 1.5 v 20 pf t thdx t tlqv t tlqx t dvth t tlth t thmx t mvth tap controller timing diagram t thth test clock (tck) test mode select (tms) test data in (tdi) test data out (tdo) t thtl
mcm69r737a ? mcm69r819a 14 motorola fast sram test access port pins tck test clock (input) clocks all tap events. all inputs are captured on the rising edge of tck and all outputs propagate from the falling edge of tck. tms test mode select (input) the tms input is sampled on the rising edge of tck. this is the command input for the tap controller state machine. an undriven tms input will produce the same result as a log- ic one input level. tdi test data in (input) the tdi input is sampled on the rising edge of tck. this is the input side of the serial registers placed between tdi and tdo. the register placed between tdi and tdo is deter- mined by the state of the tap controller state machine and the instruction that is currently loaded in the tap instruction register (refer to figure 5 tap controller state diagram). an undriven tdi pin will produce the same result as a logic one input level. tdo test data out (output) output that is active depending on the state of the tap state machine (refer to figure 5 tap controller state dia- gram). output changes in response to the falling edge of tck. this is the output side of the serial registers placed be- tween tdi and tdo. trst tap reset this device does not have a trst pin. trst is optional in ieee 1149.1. the testlogic reset state is entered while tms is held high for five rising edges of tck. power on reset cir- cuitry is included internally. this type of reset does not affect the operation of the system logic. the reset affects test logic only. test access port registers overview the various tap registers are selected (one at a time) via the sequences of ones and zeros input to the tms pin as the tck is strobed. each of the taps registers are serial shift registers that capture serial input data on the rising edge of tck and push serial data out on subsequent falling edge of tck. when a register is selected it is aplacedo between the tdi and tdo pins. instruction register the instruction register holds the instructions that are executed by the tap controller when it is moved into the run test/idle or the various data register states. the instructions are three bits long. the register can be loaded when it is placed between the tdi and tdo pins. the instruction regis- ter is automatically preloaded with the idcode instruction at powerup or whenever the controller is placed in testlogic reset state. bypass register the bypass register is a single bit register that can be placed between tdi and tdo. it allows serial test data to be passed through the rams tap to another device in the scan chain with as little delay as possible. boundary scan register the boundary scan register is identical in length to the number of active input and i/o connections on the ram (not counting the tap pins). this also includes a number of place holder locations (always set to a logic 1) reserved for density upgrade address pins. there are a total of 70 bits in the case of the x36 device and 51 bits in the case of the x18 device. the boundary scan register, under the control of the tap controller, is loaded with the contents of the rams i/o ring when the controller is in capturedr state and then is placed between the tdi and tdo pins when the controller is moved to shiftdr state. several tap instructions can be used to activate the boundary scan register. the bump/bit scan order tables describe which device bump connects to each boundary scan register location. the first column defines the bit's position in the boundary scan register. the shift register bit nearest tdo (i.e., first to be shifted out) is defined as bit 1. the second column is the name of the input or i/o at the bump and the third column is the bump number. identification (id) register the id register is a 32 bit register that is loaded with a de- vice and vendor specific 32 bit code when the controller is put in capturedr state with the idcode command loaded in the instruction register. the code is loaded from a 32 bit onchip rom. it describes various attributes of the ram as indicated below. the register is then placed between the tdi and tdo pins when the controller is moved into shiftdr state. bit 0 in the register is the lsb and the first to reach tdo when shifting begins. id register presence indicator bit # 0 value 1 motorola jedec id code (compressed format, per ieee standard 1149.1 1990 bit # 11 10 9 8 7 6 5 4 3 2 1 value 0 0 0 0 0 0 0 1 1 1 0 reserved for future use bit # 17 16 15 14 13 12 value x x x x x x device width configuration bit # 22 21 20 19 18 128kx36 value 0 0 1 0 0 256kx18 value 0 0 0 1 1 device depth configuration bit # 27 26 25 24 23 128kx36 value 0 0 1 0 1 256kx18 value 0 0 1 1 0 revision number bit # 31 30 29 28 value x x x x figure 4. id register bit meanings
mcm69r737a ? mcm69r819a 15 motorola fast sram mcm69r737a bump/bit scan order bit signal bump bit signal bump bit # signal name bump id bit # signal name bump id 1 m2 5r 36 sa 3b 2 sa 4p 37 nc 2b 3 sa 4t 38 sa 3a 4 sa 6r 39 sa 3c 5 sa 5t 40 sa 2c 6 zz 7t 41 sa 2a 7 dqa 6p 42 dqc 2d 8 dqa 7p 43 dqc 1d 9 dqa 6n 44 dqc 2e 10 dqa 7n 45 dqc 1e 11 dqa 6m 46 dqc 2f 12 dqa 6l 47 dqc 2g 13 dqa 7l 48 dqc 1g 14 dqa 6k 49 dqc 2h 15 dqa 7k 50 dqc 1h 16 sba 5l 51 sbc 3g 17 ck 4l 52 nc 4d 18 ck 4k 53 ss 4e 19 g 4f 54 nc 4g 20 sbb 5g 55 nc 4h 21 dqb 7h 56 sw 4m 22 dqb 6h 57 sbd 3l 23 dqb 7g 58 dqd 1k 24 dqb 6g 59 dqd 2k 25 dqb 6f 60 dqd 1l 26 dqb 7e 61 dqd 2l 27 dqb 6e 62 dqd 2m 28 dqb 7d 63 dqd 1n 29 dqb 6d 64 dqd 2n 30 sa 6a 65 dqd 1p 31 sa 6c 66 dqd 2p 32 sa 5c 67 sa 3t 33 sa 5a 68 sa 2r 34 nc 6b 69 sa 4n 35 sa 5b 70 m1 3r mcm69r819a bump/bit scan order bit signal bump bit signal bump bit # signal name bump id bit # signal name bump id 1 m2 5r 36 sbb 3g 2 sa 6t 37 nc 4d 3 sa 4p 38 ss 4e 4 sa 6r 39 nc 4g 5 sa 5t 40 nc 4h 6 zz 7t 41 sw 4m 7 dqa 7p 42 dqb 2k 8 dqa 6n 43 dqb 1l 9 dqa 6l 44 dqb 2m 10 dqa 7k 45 dqb 1n 11 sba 5l 46 dqb 2p 12 ck 4l 47 sa 3t 13 ck 4k 48 sa 2r 14 g 4f 49 sa 4n 15 dqa 6h 50 sa 2t 16 dqa 7g 51 m1 3r 17 dqa 6f 18 dqa 7e 19 dqa 6d 20 sa 6a 21 sa 6c 22 sa 5c 23 sa 5a 24 nc 6b 25 sa 5b 26 sa 3b 27 nc 2b 28 sa 3a 29 sa 3c 30 sa 2c 31 sa 2a 32 dqb 1d 33 dqb 2e 34 dqb 2g 35 dqb 1h notes: 1. the nc pads listed in this table are indeed no connects, but are represented in the boundary scan register by a aplace holdero bit that is forced to logic 1. these pads are reserved for use as address inputs on higher density rams that follow this pad out and scan order standard. 2. in scan mode, differential inputs ck and ck are referenced to each other and must be at opposite logic levels for reliable operation. 3. m1 and m2 are not ordinary inputs and may not respond to standard i/o logic levels. m1 and m2 must be driven to within 100 mv of a v dd or v ss supply rail to ensure consistent results. 4. zz must remain at v il during boundary scan to ensure consistent results.
mcm69r737a ? mcm69r819a 16 motorola fast sram tap controller instruction set overview there are two classes of instructions defined in the stan- dard 1149.11990; the standard (public) instructions, and de- vice specific (private) instructions. some public instructions, are mandatory for 1149.1 compliance. optional public instructions must be implemented in prescribed ways. although the tap controller in this device follows the 1149.1 conventions, it is not 1194.1 compliant because some of the mandatory instructions are not fully implemented. the tap on this device may be used to monitor all input and i/o pads, but cannot be used to load address, data or control sig- nals into the ram or to preload the i/o buffers. in other words, the device will not perform standard 1149.1 extest, intest or the preload portion of the sample / preload command. when the tap controller is placed in captureir state the two least significant bits of the instruction register are loaded with 01. when the controller is moved to the shiftir state the instruction register is placed between tdi and tdo. in this state the desired instruction is serially loaded through the tdi input (while the previous contents are shifted out at tdo). for all instructions, the tap executes newly loaded instructions only when the controller is moved to updateir state. the tap instruction sets for this device are listed in the following tables. standard (public) instructions bypass the bypass instruction is loaded in the instruction regis- ter when the bypass register is placed between tdi and tdo. this occurs when the tap controller is moved to the shiftdr state. this allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. sample/preload sample/preload is a standard 1149.1 mandatory public instruction. when the sample / preload instruction is loaded in the instruction register, moving the tap controller into the capturedr state loads the data in the rams input and i/o buffers into the boundary scan register. because the ram clock(s) are independent from the tap clock (tck) it is pos- sible for the tap to attempt to capture the i/o ring contents while the input buffers are in transition (i.e. in a metastable state). although allowing the tap to sample metastable in- puts will not harm the device, repeatable results cannot be expected. ram input signals must be stabilized for long enough to meet the taps input data capture setup plus hold time (t cs plus t ch ). the rams clock inputs need not be paused for any other tap operation except capturing the i/o ring contents into the boundary scan register. moving the controller to shiftdr state then places the boundary scan register between the tdi and tdo pins. be- cause the preload portion of the command is not imple- mented in this device, moving the controller to the updatedr state with the sample / preload instruction loaded in the instruction register has the same effect as the pausedr command. this functionality is not standard 1149.1 compliant. extest extest is an ieee 1149.1 mandatory public instruction. it is to be executed whenever the instruction register, whatever length it may be in the device, is loaded with all logic 0s. extest is not implemented in this device. therefore this device is not 1149.1 compliant. nevertheless, this rams tap does respond to an all zeros instruction, as follows. with the extest (000) instruction loaded in the instruction register the ram responds just as it does in response to the sample / preload instruction described above, except the ram outputs are forced to highz any time the instruction is loaded. idcode the idcode instruction causes the id rom to be loaded into the id register when the controller is in capturedr mode and places the id register between the tdi and tdo pins in shiftdr mode. the idcode instruction is the default instruction loaded in at power up and any time the controller is placed in the testlogicreset state. the device specific (public) instruction samplez if the samplez instruction is loaded in the instruction register, all ram outputs are forced to an inactive drive state (highz) and the boundary scan register is connected be- tween tdi and tdo when the tap controller. is moved to the shiftdr state. the device specific (private) instruction noop do not use these instructions; they are reserved for future use.
mcm69r737a ? mcm69r819a 17 motorola fast sram standard (public) instruction codes instruction code* description extest 000 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all ram outputs to highz state. *not 1149.1 compliant* idcode 001** preloads id register and places it between tdi and tdo. does not affect ram operation. sample / preload 100 captures i/o ring contents. places the boundary scan register between tdi and tdo. does not affect ram operation. does not implement 1149.1 preload function. * not 1149.1 compliant * bypass 111 places bypass register between tdi and tdo. does not affect ram operation. samplez 010 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all ram output drivers to highz. * instruction codes expressed in binary, msb on left, lsb on right. ** default instruction automatically loaded at powerup and in testlogicreset state. standard (private) instruction codes instruction code* description no op 011 do not use these instructions; they are reserved for future use. no op 101 do not use these instructions; they are reserved for future use. no op 110 do not use these instructions; they are reserved for future use. * instruction codes expressed in binary, msb on left, lsb on right. capturedr exit1dr exit2dr updatedr captureir exit1ir exit2ir updateir shiftir pauseir shiftdr pausedr testlogic reset runtest/ idle select drscan select irscan 1 0 1 1 1 1 1 1 1 11 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 note: the value adjacent to each state transition represents the signal present at tms at the rising edge of tck. 0 figure 5. tap controller state diagram
mcm69r737a ? mcm69r819a 18 motorola fast sram ordering information (order by full part number) mcm 69r819a xx x x motorola memory prefix part number full part numbers e mcm69r737azp5 mcm69r737azp6 mcm69r737azp7 mcm69r737azp8 mcm69r819azp5 mcm69r819azp6 mcm69r819azp7 mcm69r819azp8 mcm69r737azp5r mcm69r737azp6r mcm69r737azp7r mcm69r737azp8r mcm69r819azp5r mcm69r819azp6r mcm69r819azp7r MCM69R819AZP8R r = tape and reel, blank = tray package (zp = pbga) speed (5 = 5 ns, 6 = 6 ns, 7 = 7 ns, 8 = 8 ns) 69r737a
mcm69r737a ? mcm69r819a 19 motorola fast sram zp package 7 x 17 bump pbga case 99901 package dimensions l a b c d e f g h j k l m n p r t u a p n 4x 16x 119x top view k bottom view side view b s 0.20 (0.008) r 6x g g 7654321 d l 0.30 (0.012) s tw ss 0.10 (0.004) s t 0.15 (0.006) t 0.25 (0.010) t 0.35 (0.014) t e c dim a min max min max inches 14.00 bsc 0.551 bsc millimeters b 22.00 bsc 0.866 bsc c 2.40 0.094 d 0.60 0.90 0.024 0.035 e 0.50 0.70 0.020 0.028 f 1.30 1.70 0.051 0.067 g 1.27 bsc 0.050 bsc k 0.80 1.00 0.031 0.039 n 11.90 12.10 0.469 0.476 p 19.40 19.60 0.764 0.772 r 7.62 bsc 0.300 bsc s 20.32 bsc 0.800 bsc notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. pin 1a identifier f w t
mcm69r737a ? mcm69r819a 20 motorola fast sram motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. mfax is a trademark of motorola, inc. how to reach us: usa / europe / locations not listed : motorola literature distribution; japan : nippon motorola ltd.: spd, strategic planning office, 4321, p.o. box 5405, denver, colorado 80217. 13036752140 or 18004412447 nishigotanda, shinagawaku, tokyo 141, japan. 81354878488 customer focus center: 18005216274 mfax ? : rmfax0@email.sps.mot.com touchtone 1 6022446609 asia / pacific : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, motorola fax back system us & canada only 18007741848 51 ting kok road, tai po, n.t., hong kong. 85226629298 http://sps.motorola.com/mfax/ home page : http://motorola.com/sps/ mcm69r737a/d ?

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